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4.8 section Frequency ratio across DFI (DFI spec 3.1)

Scenario :PHY frequency in case of 1:2(DFI:PHY or DDR) is twice of the DFI clock. Spec says as PHY operates on higher frequency , MC has op…

Started by Maitri Thakkar

1 May 11
Reply by John MacLaren

Read commands ultilizing dfi_rddata_cs_n

Hi, In DFI 3.1: Is the figure 29 Read Commands Utilizing dfi_rddata_cs_n correct? 1. Why is the trddata_en timing is different in RDA and…

Started by Sunmon

0 May 11

Both wrdata_en and wrdata unaligned(spec 3.1)

Scenarios for 1. unaligned wrdata_en_p0 and wrdata_en_p1 but aligned wrdata_p0 and wrdata_p1 (Figure 40) 2. aligned wrdata_en_p0 and wrdata…

Started by Maitri Thakkar

0 May 2

How to use dfidata_bit_enable configuration parameter added in DFI4.0 for bits checking for read and write data

For example if my data width is 160 bits and my slice width is 16 bits, So as per read/write data enable definition one read data enable w…

Started by Shilpi Gupta

1 Apr 19
Reply by John MacLaren

Phases in dfi_cke_pN/dfi_odt_pN

Hi John, Below is a snippet from the DFI specification: "Only phases where a command is sent must be implemented and driven. The exceptio…

Started by Anand Krishna

1 Mar 27
Reply by Anand Krishna

Behavior of dfi_rddata_en if some slices are not active

Hi, Looking at the DFI 3.1 spec, I see the following (footnote to table 9): "Since all bits of the dfi_rddata_en signal are identical, t…

Started by Stephen Bond

2 Mar 1
Reply by Stephen Bond

Rd/Wr_lvl Training

Hi, Read and Write leveling trainings are common across all [LP]DDRn. Why "leveling"? What is leveling logic in PHY/DRAM? Dhaval

Started by Dhaval shah

0 Feb 15

Question about CA training

Hi, I am curious why CA training only defined for LPDDR4/3,  don't DDR4 or DDRn UDIMM require to calibrate the command address as well ? I…

Started by Zijay Tsao

4 Feb 14
Reply by Zijay Tsao


Hi all,I have two questions regarding DFI & HBM(High-Bandwidth Memory):(1)Does DFI protocol support HBM as well?(2)HBM spec. does not s…

Started by Nishant Patel

3 Feb 10
Reply by John MacLaren

dfi_reset_n phases

Hi, The DFI specification 3.0 states implementing all phases for dfi_cke and dfi_odt signals. For other control signals, this is not a man…

Started by Anand Krishna

2 Feb 9
Reply by Anand Krishna


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