The memory controller logic and PHY interface represent the two primary design elements in DDR memory systems, which are used in virtually all electronic system designs, from cellphones and set-top boxes, to computers and network routers. These two components of the memory system require a uniquely different set of engineering skills, tools and methodologies, and thus, are often developed by separate engineering teams, or are acquired from different third-party design intellectual property (IP) vendors.
Consequently, the lack of a standard interface between the two design elements has become the source of significant integration and verification costs by systems developers, memory controller vendors, and PHY providers. The goal of the DFI specification is to define a common interface between the memory controller logic and the PHY interface in order to reduce cost, time-to-market, and increase the potential for reuse of the individual components that make up the memory system.
The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries, including: ARM, Avago, Cadence, Intel, Samsung, ST Microelectronics, Synopsys and Uniquify.
The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the memory devices.